Xilinx Design Flow
Currently Xilinx provides two development platforms for FPGA and SoC users. Xilinx ISE Design Suite supports all the programmable devices from Xilinx including Zynq-7000. Xilinx Vivado Design Suite is a next generation development platform for SoC strength designs and is more geared towards system-level integration and implementation. Both of these development platforms from Xilinx are equally supported by Aldec in terms of device support, libraries support and integration with GUI. Aldec has partnered with Xilinx to make sure that all the latest devices and technology from Xilinx is supported within Aldec flow.
Device Family Support
Aldec tools support all the FPGA and SoC devices from Xilinx which includes all the devices from Virtex, Spartan, Artix, Kintex and Zynq-7000 family. Aldec also support all the devices from CPLD families which include CoolRunner and XC9500 and XC4000 families.
Users can use library compilation utility from Xilinx to compile simulation libraries themselves. Library compilation utility from Xilinx supports both Active-HDL and Riviera-PRO.
Aldec also provides pre-compiled VHDL, Verilog and EDK libraries for Xilinx devices which users can download from Aldec website anytime.
Integration with GUI
Official Xilinx document states that only ISIM and Modelsim can be launched from Xilinx environment at this time. But using a workaround, Aldec users can launch Active-HDL and Riviera-PRO from within Xilinx GUI.
Simulation of IP Cores
All the IP cores provided by Xilinx are supported by Aldec tools. Xilinx introduced P1735 encryption standard for all of its IPs in Vivado 2013.1. All the IP cores in Xilinx environment is encrypted using this standard which is supported by Aldec. Users are able to run the simulation of such IPs using Aldec tools.
Legacy Design Import
Aldec provides utilities for importing legacy schematic based designs from Xilinx Foundation Series and ViewLogic/ViewDraw series. Schematic files from the legacy projects can be imported in Aldec tools with graphics including all symbols. These imported schematic files then can be edited using the Block Diagram Editor, from which HDL code can be generated.
Simulating with Xilinx libraries:
Xilinx IP Encrypted for Aldec:
DSP co-simulation (MATLAB/Simulink):
Using Aldec as default simulator:
Simulating processor-based systems:
5 ns pin-to-pin logic delays on all pins
fCNT to 125 MHz
Large density range: 36 to 288 macrocells with 800 to6,400 usable gates
5V in-system programmable
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
90 product terms drive any or all of 18 macrocells within Function Block
Global and product term clocks, output enables, set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
Programmable power reduction mode in each macrocell
Slew rate control on individual outputs - User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
3.3V or 5V I/O capability